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REV. B
AD1837
–5–
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
t
TBD
t
FSD
t
TABDD
t
TDDS
t
TDDH
TDM256 MODE (Slave)
f
AB
t
TBCH
t
TBCL
t
TFS
t
TFH
t
TBDD
t
TDDS
t
TDDH
AUXILIARY INTERFACE
t
AXDS
t
AXDH
f
ABP
Slave Mode
t
AXBH
t
AXBL
t
AXLS
t
AXLH
Master Mode
t
AUXBCLK
t
AUXLRCLK
BCLK Delay
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
20
5
10
ns
ns
ns
ns
ns
From MCLK Rising
From BCLK Rising
From BCLK Rising
To BCLK Falling
From BCLK Falling
15
15
BCLK Frequency
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
256 f
S
15
15
10
10
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling
From BCLK Falling
From BCLK Rising
To BCLK Falling
From BCLK Falling
10
15
15
AAUXDATA Setup
AAUXDATA Hold
AUXBCLK Frequency
10
10
64 f
S
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
15
15
10
10
ns
ns
ns
ns
To AUXBCLK Rising
From AUXBCLK Rising
AUXLRCLK Delay
AUXLRCLK Delay
15
15
ns
ns
From MCLK Rising
From AUXBCLK Falling
Specifications subject to change without notice.
MCLK
t
MH
PD/RST
t
ML
t
PDR
Figure 1. MCLK and
PD
/
RST
Timing
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